Logical effort designing fast cmos circuits pdf download

Single input pulse voltage waveforms. The complete current waveform obtained by sum- ming up these components is plotted in Fig. Specially, current peaks are quite accurately reproduced. The second example simulates a pulse train applied at the input of the chain. In this case, the pulses are narrow enough to degrade from logic level to logic. However, a conventional delay model CDM would propagate the full pulse train unaltered Fig.

This behaviour and its implication on the switching activity has been reported in detail in [16, 18]. In particular, current peaks are again very accurately determined. Pulse train current waveforms. It has been demonstrated that, despite its simplicity, the proposed model provides with accurate results while keeping the speed up of logic-level over electrical simulation 2 to 3 orders of magnitude.

The combination of the DDM and logic-level current models appears as a good alternative to current estimations and derived applications at the logic level. References 1. Arts and et al. Bruno, A. Macii, and M. Seen, J. Laurent, N. Julien, and M. Lattanzi, A. Acquaviva, and B. Jimenez, P. Parra, P. Sanmartin, and A. Abbo, R. Kleihorst, V. Choudhary, and S. Bogliolo, L. Benini, G. De Micheli, and B. Nikolaidis and A. Baena, J. Juan, M. Bellido, P. Ruiz-de Clavijo, C.

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Thank you. The input capacitance of the inverter is likewise proportional to the transistor widths, but with a different constant of proportionality characteristic of transistor gate capacitance. This quantity can be measured from test circuits, as shown in Section 5. We can estimate the parasitic delay of logic gates from the inverter parameters.

The delay will be greater than that of an inverter by the ratio of the total width of diffused regions connected to the output signal to the corresponding width of an inverter, provided the logic gate is designed to have the same output drive as the inverter. For this estimate to apply, we assume that transistor layouts in the logic gates are similar to those in the inverter. Note that this estimate ignores other stray capacitances in a logic gate, such as contributions from wiring and from diffused regions that lie between transistors that are connected in series.

The parasitic estimation has a serious limitation in that it predicts linear scaling of delay with number of inputs. In actuality, the parasitic delay of a series stack of transistors increases quadratically with stack height because of internal diffusion and gate-source capacitances. The Elmore delay model [9] handles distributed RC networks and shows that stacks of more than about four series transistors are best broken up into multiple stages of shorter stacks.

Since parasitics are so geometrydependent, the best way to find parasitic delay is to simulate circuits with extracted layout data. The logical effort per input for a particular input is the ratio of the capacitance of that input to the total input capacitance of the reference inverter.

The total logical effort of the gate is the sum of the logical efforts of all of its inputs. In contrast to the weak dependence on , the logical effort of a gate depends strongly on the number of inputs. When an additional input is added to a NAND gate, the logical effort of each of the existing inputs increases through no fault of its own.

Thus the total logical effort of a logic gate includes a term that increases as the square of the number of inputs; and in the worst case, logical effort may increase exponentially with the number of inputs. When many inputs must be combined, this non-linear behavior forces the designer to choose carefully between single-stage logic gates with many inputs and multiple-stage trees of logic gates with fewer inputs per gate. Surprisingly, one logic gate escapes super-linear growth in logical effort—the multiplexer.

This property makes it attractive for high fan-in selectors, which are analyzed in greater detail in Chapter The logical effort of gates covers a wide range. The XOR circuit is also messy to lay out because the gates of its transistors interconnect with a criss-cross pattern. Are the large logical effort and the difficulty of layout related in some fundamental way? Whereas the output of most other logic functions changes only for certain transitions of the inputs, the XOR output changes for every input change.

Is its large logical effort related in some way to this property? The designs for logic gates we have shown in this chapter do not exhaust the possibilities. In Chapter 8, logic gates are designed with reduced logical effort for certain inputs that can lower the overall delay of a particular path through a network. In Chapter 9, we consider designs in which the rising and falling delays of logic gates differ, which saves space in CMOS and permits analysis of ratioed NMOS designs with the method of logical effort.

How big should the transistors be? What is the logical effort of the new circuit? What relative transistor sizes should be used? What is the logical effort of the gate? A different design will be required for stages that accept a complemented carry input and generate a true carry output.

Design such a circuit and calculate the logical effort of each input. Express the best pullup and pulldown transistor sizes in an inverter as a function of to obtain minimum delay in a two-inverter pair. Consider rising and falling delays separately. Under what circumstances is each perferable?

Compare the logical effort of the two circuits. Under whiat circumstances is each perferable? Chapter 5 Calibrating the Model One can calculate the logical effort and parasitic delay of a logic gate from simple transistor models, as in the preceding chapter, or can obtain more accurate values by measuring the behavior of suitable test circuits.

This chapter shows how to design and measure such circuits to obtain the two parameter values. The reader who wishes to skip this chapter may wish to glance at Table 5. Figure 5. The measurements are an independent verification of the linear delay model on which the method of logical effort is based. The illustration shows four data points at different values of electrical effort, fitting a straight line very well. Results from 0. This figure presents delay along the vertical axis in units of , using the value of computed from Figure 5.

As a result, the slope of the fitted line will be the logical effort of the NAND gate and the intercept will be its parasitic delay. Similar simulations will calibrate an entire family of logic gates; some results are shown in Table 5. Notice that the logical effort of NOR gates agrees fairly well with our model, but that the logical effort of NAND gates is lower than predicted.

This can be attributed to velocity saturation, as discussed in Section 4. The parasitic delay depends on layout and on the order of input switching. These effects are discussed later in this chapter. The values in these figures and table were obtained through simulation.

The remainder of this chapter discusses methods and pitfalls of logical effort characterization. The vertical axis is marked in units of.

Such a circuit has two major problems. It does not account for the input slope dependence of delay, and it neglects the nonlinearity of MOS capacitors. A better test circuit is shown in Figure 5. The circuit is divided into four stages. The first two stages are responsible for shaping the input slope.

The third stage contains the gate being characterized. The final stage serves as a load on the gate. Each stage contains a primary gate a , a load gate b , and a load on the load c! Gate c is necessary because of gate-drain overlap capacitance. If gate c were removed, the output of gate b would switch very rapidly. Because of the Miller effect, this would increase the effective input capacitance to gate b.

Which should we use? In Section 9. Therefore, we normally define the logical effort and parasitic delay of a gate to be the average of the values from the rising and falling transitions. Occasionally it is useful to do a case analysis, considering rising and falling delays separately. The logical effort and parasitic delay for rising and falling transitions can be found from a curve fit in just the same way as for average delay.

The results should still be normalized to the average delay of an inverter. Our estimates of logical effort from Chapter 4 assumed that when transistors are in parallel exactly one turns on, while when transistors are in series, all series transistors turn on simultaneously to give a resistance of through each.

In contrast, real circuits tend to be modeled with a single latest input which arrives after all other inputs have settled. This leads to lower effective resistance through series transistors because the transistors with early inputs are fully turned on when the late input arrives and thus provide more current.

Which of the two or more inputs to a logic gate should we choose as the late input? It turns out that the inputs have distinct properties, so we could find the logical effort and parasitic delay parameters for each input separately. The variation of logical effort and parasitic delay with different choices of input signal is tabulated in Table 5.

An input signal is identified by a number that records the largest number of transistors between the transistors controlled by the signal and the output node of the logic gate, as shown in Figure 5.

Signal 0 connects to two transistors that have drains connected directly to the output node. Signal 1 connects to two transistors, one of which is connected to the output node, but the other is one transistor away from the output node. Signal 0 is called the innermost signal, while signal is the outermost.

On the other hand, when the outer input e. Discharging this capacitance diverts some output current and increases the parasitic delay. Indeed, parasitic delay from the outer input scales quadratically with the number of inputs as discussed in Section 4.

On account of parasitic delay, it is usually best to place the latest arriving signal on input 0. Multiple-input gates also have somewhat lower logical effort than computed in Chapter 4 because only one input is switching, as we have seen in Table 5.

The other transistors have already turned on and have a lower effective resistance than the switching transistor. If inputs to series transistors arrive simultaneously, the logical effort will be greater than these simulations have indicated.

These dimensions are shown in Figure 5. The diffusion perimeter measures only the length of the junction between the diffusion region and the substrate; the boundary between diffusion and channel is not counted, because the diffusion wall capacitance at the edge of the transistor gate is deliberately reduced by the fabrication process.

Diffusion area and perimeter depend on layout. Diffusion nodes which contact to metal wires are larger than diffusion areas between series transistors without contacts. Good layouts share diffusion nodes wherever possible. Large cells can further reduce diffusion by folding transistors. Ideally, wire capacitance should also be included in the parasitic estimate.

This can be done by extracting parasitic values from actual cell layouts. The parasitic delays reported in this chapter include realistic diffusion capacitances, but omit wire capacitance. Ideally, logical effort of a gate would be independent of process parameters, as was found in Chapter 4. In reality, effects like velocity saturation cause logical effort to differ slightly with process and operating conditions.

Table 5. Similarly, parasitic capacitance differs with process and environment. In such a case, logical effort can still be estimated from vendor datasheets or measured from test chips. Some cell libraries come with delay vs. Logical effort can easily be extracted from the delay vs. Logical effort can also be measured from fabricated chips by plotting the frequency of ring oscillators. The oscillator should contain an odd number of inverting stages.

The frequency of the ring oscillator is related to the delay of the gate, as was discussed in Example 1. Oscillators with different fanouts provide data for the delay vs. Care should be taken to load the load gates suitably to avoid excessive Miller multiplication of the load capacitance. Also, fabricated chips will include wire capacitance, which may have been neglected in simulation.

Finally, the output should be tapped off one of the load gates to avoid extra branching effort on the ring oscillator. Unfortunately, this is not possible in rings built from fanout-of-1 gates. Unfortunately, the techniques break down for other circuit families. For instance, a dynamic gate cannot directly drive another dynamic gate because the monotonicity rule would be violated.

If gates are skewed to favor a critical transition, the edge rate of the other transition is unrealistically slow and should not be used to set the input slope. Dynamic gates have a very low switching threshold. If the slope of the input is slow, dynamic gates may even have a negative delay. A better approach is to characterize the delay of the dynamic gate and subsequent inverter as a pair.

Remember to use an electrical effort for the pair equal to the produce of the electrical efforts of each stage. Initial estimates of logical effort can be used to determine the size of the static gate such that the stage effort of the dynamic and static gate are approximately equal. Static gates are sometimes skewed to favor a particular transition, as will be discussed in Section 9. For example, a high-skew gate with a larger PMOS transistor may be used after a dynamic gate.

Characterizing a chain of identical skewed gates also leads to misleading results. We would like to characterize the logical effort of the rising output of a high-skew gate because that is the delay which would appear in a critical path. If a chain of such skewed gates is used, the input slope will come from a falling transition and will be unreasonably slow.

This retards the rising output as well. To avoid this problem, characterize skewed gates as part of a unit, just as recommended for dynamic gates. The results suggest that the calculation methods described in Chapter 4 are good, but that somewhat greater accuracy and confidence can be obtained from more detailed calibrations. Since the logical effort and parasitic delay of gates change only slightly with process, is a powerful way to characterize the speed of a process with a single number.

Parasitic delay varies more than logical effort, but since effort delay usually exceeds parasitic delay, the variation is a smaller portion of the overall delay. How well do the numbers agree with the estimates from Chapter 4 and the measurements in this chapter? What general advice can you extract from your plot? When a logic signal divides within a network and flows along multiple paths, we must decide how to allocate the input current.

How much should each path load the common input? When a logic signal has significant parasitic capacitance, for example when it drives a long wire, it branches: as some of the signal is diverted to charge the parasitic load, less drive is available to the logic path.

Optimizing networks that branch usually involves adjusting branching effort along paths to equalize the delays in several paths through the network. Determining the branching factors adds a new element of difficulty to our design method that can be quite tricky to handle.

One of the complications is that different paths through a network often have different numbers of stages. Branching can sometimes be straightforward, depending on the design problem. For example, branching is simple in the synchronous arbitration problem of Section 2. This chapter covers a simple but common case of branching: generating the true and complement forms of a logic signal. Forks are interesting not only for their own utility, but also as a further exercise in applying the method of logical effort.

Many CMOS circuits require forks to produce such true and complement signals. For example, an arm of the multiplexer circuit of Figure 4. The XOR circuit shown in Figure 4. L Figure 6. One leg inverts the input signal and one does not. One of the strings contains an odd number of inverters and the other contains an even number. True and complement signals of this kind, particularly for driving multiplexers, are often required at relatively high power levels. For example, if an entire word consisting of 64 bits is to be multiplexed onto a bus, the true and complement signals for the entire word must drive 64 multiplexers.

As we have already learned, least delay in driving such large loads will be obtained by including the proper number of amplifying inverters in the drive path. The figure illustrates a notation we use when the exact number of inverters in each path is not known: an inverter symbol with a star inside it represents a string of an odd number of inverters, while a triangle symbol with an embedded star but without the small circle at its output stands for an even number of inverters.

We have chosen to name forks by the number of amplifiers in each string. A fork, for example, has three amplifiers in one string and two in the other. Figure 6. It is useful to think of pairs of amplifier strings as a fork only when the true and complement output signals must emerge at the same time. The driver for the address lines in Figure 2. We therefore wish to design forks so that the delay in each leg is the same. In this chapter we shall assume that the load driven by each leg of the fork is the same.

A fork that drives an XOR gate such as that of Figure 4. A multiplexer like the 6. We shall defer to Chapter 7 consideration of circuits with multiple outputs driving different load capacitance but see Exercise The design of a fork starts out with a known load on the output legs and known total input capacitance. As shown in Figure 6. Even if the load capacitances on the two legs of the fork are equal, it is not in general true that the input capacitances to the two legs of the fork are equal.

Because the legs have a different number of amplifiers but must operate with the same delay, their electrical efforts may differ. Either leg of the fork can be made faster by reducing its electrical effort, which is done by giving it wider transistors for its initial amplifier. Doing so, however, takes input current away from the other leg of the fork and will inevitably make it slower.

A fixed value of provides, in effect, only a certain total width of transistor material to distribute between the first stages of the two legs; putting wider transistors in one leg requires putting narrower transistors in the other leg. The task of designing a minimum delay fork is really the task of allocating the available transistor width set by to the input stages of the two legs. What is the total delay of the fork? The remainder is allocated to the 1-inverter leg.

We want to find the value of that will equalize delays in the two legs. Applying Equation 1. Thus, the two legs have equal delay as expected. Note that This equation solves to this delay is less than the delay we computed for the fork with the same input and output capacitances.

These two examples show that obtaining the least delay requires choosing the right number of stages in the fork. This result is not surprising. This result suggests that we should develop a method to determine the best number of stages to use in a fork. The next section turns to this problem. An optimized fork must have legs that differ in length by at most one stage. We can see that this is true by examining in detail the relationship between total delay and electrical effort that was discussed in Chapter 1.

The thick curve represents the fastest possible amplifier for any given electrical effort, and so no amplifier design may lie below it. For different electrical efforts, different numbers of stages are required to obtain this optimum design, as the figure shows.

The task of designing a fork is specified by giving an electrical effort that the combined activities of its two legs are to support. In Figure 6.

One possible design for the fork requires each leg to support exactly this electrical effort. Since the two legs of the fork must produce true and complement signals, their lengths must differ by an odd number of inverters.

Thus we have a fork with two legs that support equal electrical effort but have unequal delay. We do this by reallocating transistor width from the transistors of the first amplifier in one leg to the transistors of the first amplifier in the other leg.

Our intent, of course, is to decrease the delay of the slower leg as much as we can, which will be until the two legs are equal in delay. One might think that there are two possible discontinuities in the process of reallocating the input transistor width. It is not hard to see that for any placement of the given electrical effort line, this optimization procedure will result in a fork with legs that differ in length by a single amplifier.

One leg of a fork will always have exactly the same number of stages as would an optimum amplifier supporting an equal electrical effort.

This is easy to see from Figure 6. Thus one simple way to design nearly optimal forks is to choose the number of stages for one leg from Table 1. A more precise guide for choosing the number of stages in a fork appears in Table 6.

For any given electrical effort, the table shows what kind of fork to use. Remember that the electrical effort of the fork is the total load of all the legs divided by the total input capacitance. The break points in Table 6. It is easy to see that this must be so.

There are certain electrical efforts, namely 5. Obviously, for an electrical effort of In these special cases, moreover, the input capacitance to the legs will also be identical. For some electrical effort between This is the break point recorded in Table 6. It is easy to see how Table 6. Consider the break point where a fork and a fork provide identical results.

At this break point the two forks exhibit identical delays. The three-amplifier legs in each fork must be identical. Moreover, the amount of input current left over from the three-amplifier leg in each fork must also be the same, and thus the input currents of the two-amplifier leg in one fork and the four-amplifier leg in the other fork must also be the same.

Thus at the break point between and forks, the electrical effort of the twoamplifier leg and of the four-amplifier leg must be the same, and they are operating with identical delays.

In terms of Figure 6. This reasoning leads directly to equations that can be solved to find the electrical effort of optimal forks at these break points see Exercise Example 6. The first stage of the path can present an input capacitance of twelve unit-sized transistors and the tri-state drivers are each 6 times unit size.

A unit sized tri-state is shown in Figure 6. From Table 6. Now we must divide the input capacitance between the two legs. If the 4-inverter leg gets a fraction , then we have: 6. Therefore, the capacitances of each gate can be computed, as shown in Figure 6. One may well ask whether to prefer an fork to a string of 8 amplifiers followed by a fork.

In fact, there is little to be gained by using forks with more than amplifiers; this is quantified in Exercise On the other hand, long strings of amplifiers will no doubt contain very large transistors that will be laid out in sections anyway.

Thus the layout penalty of a long fork may be small. Ironically, the most difficult case occurs when very small amplification is required. Exercise examines the performance penalty of forks. Rather than use a fork, it is better to use a fork and, if necessary, remove a stage somewhere else in the network. EXERCISES difficult to solve, two of the techniques shown in this chapter apply to more complex branching problems covered in the next chapter: The path effort of a network, measured as the total load capacitance divided by the input capacitance, can be used to estimate the correct number of stages to use.

In the case of amplifier forks driving equal loads, we have shown that the number of stages in the two paths is nearly the same. However, as we shall see in more general cases that have different efforts along different paths, the lengths of different paths in a network may differ substantially. Many multiplexers may be driven by the same logic signal, resulting in a very large load.

Modify the analysis of this chapter to apply to these forks, assuming the load on the leg with an odd number of stages is twice the load on the leg with an even number of stages; note that this assumption is equivalent to saying that the higher load must be driven by a signal that is the logical complement of the input to the fork. Build a table analogous to Table 6. Solve them and verify that your answers match those of the table. How far does this strategy depart from the optimum fork designs?

If each of the load capaitances is times as large as the input capacitance, what are the delays of the original and improved designs? The first uses a fork, while the other avoids this structure. Compare the delays of the two designs over a range of plausible electrical efforts. Is the first design ever preferred? Chapter 7 Branches and Interconnect Logical effort is easy to use on circuits with easily computed branching efforts.

For example, circuits with a single output or a regular structure are easy to design. Real circuits often involve more complex branching and fixed wire loads. There is often no closed-form expression for the best design of such circuits, but this chapter develops approximations and iterative methods that lead to good designs in most cases.

Designing networks that branch requires not only finding the best topology for the network, but also deciding how to divide the drive at a branch so that delays in all paths are equalized. In this chapter, we build on the previous results to handle more general cases. We shall consider circuits with two or more legs, where each leg may contain a different number of stages, each leg may perform a different logic function, and each leg may drive a different load.

As one might guess, we can combine the logical and electrical efforts associated with each leg to obtain a composite effort on which to base our computations. The simplicity of the forks considered in the previous chapter makes it possible to choose their topology from a table on the basis of the overall electrical effort imposed on the fork. In this chapter we will consider a more complex and varied set of circuits.

We will use the theory of logical effort to write equations that relate the size of individual logic elements to their delay. By balancing the delay in the various legs of the circuit, we will be able to reduce the delay in the worst path. These examples are generalizations of forks of amplifiers.

Next, we turn to an exclusive-or network that involves not only branching but also recombination of signals within the network. Interconnect presents new problems because the capacitance of the wire does not scale with gate size. However, circuits with interconnect can be analyzed on a case by case basis. We close the chapter with an outline of a general design procedure for dealing with branching networks.

Although it is possible to formulate network design problems as a set of delay equations and solve for a minimum, the method of logical effort often provides simple insights that yield good designs without a lot of numerical work. If necessary, these initial designs can be adjusted based on more detailed timing analysis.

We will start with simple circuits that branch immediately at a single input, and postpone to later circuits with logic functions preceding a branch point. Such circuits are very similar to the forks of Chapter 6, except that we shall now consider also unequal loading on the outputs and unequal logical effort in the legs.

It shows that the input drive should be allocated in proportion to the electrical effort borne 7. Once we have determined how to allocate the input capacitance, we can calculate transistor sizes for each path independently. What happens if the paths include logic, rather than simply inverters?

In other words, the input capacitance should be and allocated in proportion to the total effort borne by each path. Even more importantly, the entire configuration of Figure 7. The important point is that the equivalent configuration has no branch; the effect of the branch has been captured by summing the efforts of the two paths.

This property allows us to analyze branching networks by working backward from the outputs, replacing branching paths with their single-path equivalents. This stage effort is the same for all legs of the branch. This is a powerful technique for designing networks with branches, as illustrated in the following example. Starting at the output and working backward, we find gate input capacitances of 36, 31, and 9 for the inverter, NOR, and NAND, respectively.

Working backward, we find input capacitances of 48, 12, and 3, respectively. Although we had attempted to size each leg for equal delay, the different parasitics result in different delays. To equalize delay, a larger portion of the input capacitance must be dedicated to the top leg with more parasitics.

Even when this is done, however, the delay of each path is This example illustrates a general problem: unequal parasitics damage Equation 7. Sometimes the difference in parasitic delays is small, and our previous analysis is very nearly correct. Even if the difference is large, as it was in the 7. If differences in parasitic delay are too great, we can use our analysis to find an initial design, but to get the best design, we will need to adjust the branching allocation.

Usually, this is simply a matter of making accurate delay calculations for each path, and modifying the branching allocation slightly. In all cases, assuming zero parasitic delay leads to a pretty good design that can then be refined by more accurate delay calculations and adjustments. A spreadsheet program is a handy tool for making such calculations. We will revisit their analysis here to introduce the problem of designing arbitrary branching networks.

As a first example, consider the simple case of a fork with unequal loading, as shown in Figure 7. We use similar conventions as in Figure 7. Recalling Equation 1. The analysis generalizes easily to a fork with three paths as shown in Figure 7. First of all, assuming that all three legs of the fork of Figure 7.

There is not, for the same reason that it is pointless to make the two legs of a simple fork differ in length by more than one. Of course, our example involves only inverters, and we want to consider cases where each leg contains a logic function as well. When there are logic functions involved, one might argue that the particular logic functions require the given number of stages. That may be a valid argument for preserving the three-stage leg, because there may be logic functions that can be done with less logical effort in 3 stages than in a single stage.

We will think it unusual, therefore, to find a least delay circuit whose legs differ in length by more than one. An important exception arises when the problem is constrained by minimum drawn device widths. This simplifies the equations for allocating input capacitance: we will have at most two equations like Equation 7.

Moreover, because logical and electrical effort are interchangeable, all these branching problems are equivalent to designing amplifier forks, covered in Chapter 6. Note, however, that when we model parasitic delay properly, collapsing paths of equal length but different parasitic delay may introduce errors.

In summary, circuits with a single input and multiple outputs can be analyzed as forks, except that the effective load capacitance on each output must be increased by the logical effort of the leg driving it. Because the minimum delay circuits will generally have paths of nearly the same length, a good approximation to their performance can be obtained by assuming that all paths are the same length, summing the path efforts, and analyzing the entire network as a single path.

We learned in Section 3. A good first approximation, therefore, lumps all the effort of the network for choosing a suitable path length. One common form of circuit contains a logic element followed by a fork, as shown in Figure 7. If both sides of the fork had two stages, a per stage delay of 2 would be best, and the overall delay would be 6. One side of the fork, however, has only one stage instead of two.

One might think that because of the similarity of a single inverter with stage delay of 4 to a pair with stage delays of 2 each substituting the single inverter for two to make the fork would leave the stage delay unchanged. Solving Equation 7. In other words, a slightly faster circuit can be obtained by using more time in the logic element and less in the fork, with an overall delay of 5.

This is not entirely unreasonable because the single amplifier leg of the fork is not as good at driving heavy loads as is the two amplifier side. Here three stages are more obviously required. For such circuits, least delay will be obtained with a stage delay in the early circuitry that lies between the stage delay of the longer leg of the fork and the stage delay of the shorter leg of the fork. As the number of stages grows larger, the influence of one stage more or less on the overall delay becomes less, as we learned in Section 3.

If more accurate results are desired, it is easy to write equations similar to those in the figures for any particular case. The solution of such equations leads to the fastest design. Such circuits can be analyzed in the same way as we have done with the previous examples. Where optimization is required, these expressions can be differentiated.

An interesting example of such a circuit is the form of XOR shown in Figure 7. While this circuit has only one output, its early stages branch and recombine in a way that requires an analysis similar to others in this chapter. The topology of this circuit involves both some paths with three stages and some paths with two stages. The output of the first stage recombines with direct inputs at the second stage. Our interest in this example lies in learning how to analyze it and in understanding the resulting delays.

We will solve this example three times. Third, as a thought experiment, we shall add mythical non-inverting amplifiers to the circuit, as indicated by the dotted symbols in the figure.

Although such amplifiers are not realizable, it will be instructive to study the changes that they would cause to circuit performance by providing three stages in each path.

Notice that the delay is distributed unequally to the three stages; the first stage operates with less delay, and the remaining two with more delay than when all three delays were forced to be equal. Notice that the first stage operates in parallel with the direct connection from the inputs to the second stage.

Since the direct connection is not an amplifier, it pays to provide more amplification in later stages by making them operate relatively more slowly.

Why is this a reasonable assumption?